1. Field of the Invention
The present invention relates to a semiconductor. apparatus capable of reducing to a minimum a wiring delay of an input signal in an integrated circuit in which a plurality of logic circuits are arranged in the same direction, thereby achieving high-speed operations.
2. Description of the Related Art
In semiconductor apparatus such as IC and LSI, a plurality of logic circuits of the same structure are, in most cases, arranged on a substrate in the same direction.
A general semiconductor memory apparatus such as an SRAM comprises two parts: a part wherein a plurality of logic circuits of the same structure, e.g. memory cell arrays, row decoders/column decoders, section decoders and section amplifiers, are arranged in the same direction on the most area of a semiconductor substrate (i.e. chip), and a part surrounding the chip, wherein address buffers, control signal buffers and data input/output (I/O) buffers are arranged.
Normally, signals are transmitted among the logic circuits via a single metal wiring layer or multiple metal wiring layers formed on the chip.
The metal wiring layers are arranged so that the wiring area may reduce to a minimum in consideration of the influence on the chip size. In addition, the metal wiring layers are arranged to have a minimum length in consideration of the influence of parasitic capacitance C and/or parasitic resistance R upon signals.
FIG. 1 shows an example of a circuit constituting a semiconductor memory. Specifically, FIG. 1 shows arrangement of metal wiring for connecting an address buffer 6, a row decoder 3 and a decoder control circuit 9. The number of address buffers 6 is equal to the number (N) of addresses, and each address buffer 6 outputs a signal A/A (A is a complimentary signal of signal A). The decoder control circuit 9 outputs a control signal EN for the decoder. In the row decoder 3, a 2.sup.N -number of logic circuits (51, 52, . . . , 5m) having (N+1) inputs are arranged in the same direction, and input terminals of each logic circuit are supplied with an address signal A/A and a control signal EN.
In these metal wirings, parasitic capacitance C and parasitic resistance R are present as distributed constants, and a delay of input signals occurs. Such a delay of input signals further increases since an input capacitance at each input terminal functions as a load.
The degree of propagation delay of the output A/A increases as it reaches, or input to, a point farther from the address buffer 6, i.e., in the order from a point a at an output terminal of a driver provided within the buffer 6, a point b at an input terminal of the logic circuit 51 closest to the address buffer 6, and a point c at an input terminal of the logic circuit 5m remotest from the address buffer 6.
FIGS. 2 and 3 are characteristic graphs illustrating delay states of the input signals at the points a, b and wherein c. The number of arranged logic circuits constituting the row decoder 3 increases in accordance with an increase in memory capacity, and the propagation delay from the point b to point c increases accordingly.
In a signal line for transmitting a control signal EN from the decoder control circuit 9, similar propagation delay occurs with respect to the control signal EN input to a point d at an output terminal of a driver provided in the decoder control circuit 9, a point e at an input terminal of the logic circuit 5m closest to the decoder control circuit 9 and a point f at an input terminal of the logic circuit 51 farthest from the decoder control circuit 9. The propagation delay has considerable influence upon the circuit operation.
Such influence of propagation delay upon the circuit operation will now be described with reference to FIG. 4.
Suppose that the decoder control signal EN is changed from a high (H) level to a low (L) level at point d by the driver of the decoder control circuit 9. At this time, owing to the aforementioned wiring delay, the control signal EN is changed from H level to L level with a delay at point f.
There are two cases where the output A/A of the address buffer 6 changes from L level to H level and it changes from H level to L level. When the output A/A has changed from L to H, it is possible that the level of the output A/A may temporarily change from L to H to L at the logic circuit 5 of the row decoder 3 and the decoder 3 may be activated. In order to avoid this, the output A/A of the address buffer 6 is changed after the control signal EN has been completely changed from H to L at point f.
In the case where the output A/A of the address buffer 6 has changed from H to L, too, the output level changes from H to L with a delay at point c at the input terminal of the logic circuit 5m owing to the wiring delay.
The decoder control signal EN is changed from L to H after the output A/A has been completely changed from H to L at point c. This is intended to prevent the decoder 3 from being temporarily activated when the output level is changed from L to H to L at the logic circuit 5m of the row decoder 3.
As has been described above, the row decoder 3 is activated when the decoder control signal EN is changed from L level to H level. At this time, of course, the change of level of the decoder control signal from L to H is delayed by the wiring delay at point f, and the logic circuit 51 of the row decoder 3, which has the input terminal at point f, is activated lastly.
As has been described above, the time needed until the row decoder 3 is activated is determined by the wiring delay. The greater the wiring delay, the longer the time needed for the activation of the row decoder 3. In particular, as is shown in FIG. 1, if the address buffer 6 for generating the input signal is arranged in an outside area which does not overlap an area extending in a direction perpendicular to the direction of arrangement of the logic circuits of the row decoder 3, the difference in distance between the input terminal of the logic circuit situated close to the address buffer 6 and the input terminal of the logic circuit situated away from the address buffer 6 results in a difference in wiring delay. The greater the wiring distance, the more the high-speed operation of the semiconductor apparatus becomes difficult.